Supported Devices: UltraScale+
Encrypted Netlist: NO
IP Format: Encrypted Netlist
Product Description
Developed based on AMD/Xilinx 100G Ethernet MAC IP, MTU supports up to 9000 bytes of data transmission, standard AXI4 Stream interface, supports AMD/Xilinx Zynq UltraScale+ RFSoC, Zynq UltraScale+ MPSoC, Virtex UltraScale+, Kintex UltraScale+, Artix UltraScale+ Series FPGA devices. The 100G Ethernet with high bandwidth and low latency ensures fast data transmission and real-time processing, while the UDP protocol stack further improves the efficiency and accuracy of data transmission.
We provide you with a fast, reliable, low-cost, and high-performance solution that significantly shortens the time to market and is suitable for high bandwidth, low latency, and high-speed data transmission scenarios.
Applications
? Data Center
? Cloud Computing Storage
? AI
? Machine Learning
? Telecommunications
? Industrial Automation
? Internet of Things
? Medical
? Gene Sequencing
? 4K/8K HD Video Transmission
? Scientific Research Experiment
? Financial Transactions
? Test Measurement
Key Features
? Implement an ARP/IPV4/ICMP/UDP protocol stack that complies with the IEEE802.3 standard based on the OSI layered model.
? Supports ARP for obtaining or sending MAC addresses.
? Supports ICMP for responding to Ping commands.
? ARP responds to all incoming requests, only stores 10 ARP tables.
? No UDP packets are sent if the ARP table is not established.
? 100Gbps Ethernet connection, supporting UDP/IP checksum processing, calculating CRC by the MAC IP.
? Developed based on AMD/Xilinx 100G MAC IP, supporting MTU up to 9000 Bytes and a minimum 64 Bytes data transmission size.
? AXI4 Stream interface for users, with the protocol stack using a clock of 322.266 MHz generated by the MAC IP, and a 100 Gbps data bus width of 512 bits.
Example of Application Structure Diagram
The diagram below shows the position of the 100G Ethernet UDP/IP Protocol Stack FPGA IP Core within the system design:
The 100G Ethernet UDP/IP Protocol Stack FPGA IP Core uses standard AXI4-Stream interfaces for both the user interface and the Ethernet MAC + PCS/PMA IP interface. The Ethernet MAC + PCS/PMA can be any third-party IP. In the provided design example, AMD/Xilinx 100G Ethernet Subsystem IP is used.
IP Resource Utilization Table
The evaluation of IP resource consumption adopts AMD Kintex UltraScale+ series FPGA Development Kits/boards, which provides a fully functional design platform for building communication centric Ethernet applications. The AMD Kintex UltraScale+ series FPGA development boards/Kits provides an out of the box hardware platform with reference designs, which can shorten development time and allow you to focus on your target applications.
| Chip Model | Device Series | Frequency (MHz) | CLB Regs | CLB LUTs | CLB | BRAM Tile | URAM | Design Tools | |||
|---|---|---|---|---|---|---|---|---|---|---|---|
| XCKU15P-FFVE1517 | Kintex UltraScale+ | 322.266 | 27711 | 17586 | 3687 | 26 | 0 | Vivado 2020.1 | |||
Note: Actual IP resource consumption is affected by the consumption of other logical resources during instantiation.
What do we offer?
There are two licensing methods available for our IP cores
Licensing Types:
One-Time License: Unlimited usage for a specific Xilinx FPGA series (e.g. 7 Series, UltraScal. UltraScale+). Not tied to a specific PC, No MOQ.
DNA Activation Code: Tied to each FPGA chip's unique DNA: licensed per unit. Suitable for low-volume customers, MOQ applies.
Security & Traceability:
Each IP core includes a customer-specific internal code distribution or leakage.
